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IR3841MPbF
Figure 3c. shows the recommended startup
sequence for sequenced operation of IR3841
with Enable used as logic input.
Fig. 5. Pre-Bias startup pulses
Soft-Start
The IR3841 has a programmable soft-start to
control the output voltage rise and to limit the
current surge at the start-up. To ensure correct
start-up, the soft-start sequence initiates when
the Enable and Vcc rise above their UVLO
thresholds and generate the Power On Ready
(POR) signal. The internal current source
( 1.4 - 0.7 ) * C SS
T start = - - - - - - - - - - - - - - - - - - - - (1)
Fig. 3c. Recommended startup sequence,
Sequenced operation
Pre-Bias Startup
IR3841 is able to start up into pre-charged
output, which prevents oscillation and
disturbances of the output voltage.
The output starts in asynchronous fashion and
keeps the synchronous MOSFET off until the first
gate signal for control MOSFET is generated.
(typically 20uA) charges the external capacitor
C ss linearly from 0V to 3V. Figure 6 shows the
waveforms during the soft start.
The start up time can be estimated by:
20 μ A
During the soft start the OCP is enabled to
protect the device for any short circuit and over
current condition.
Figure 4 shows a typical Pre-Bias condition at
start up.
The synchronous MOSFET always starts with a
narrow pulse width and gradually increases its
duty cycle with a step of 25%, 50%, 75% and
100% until it reaches the steady state value. The
number of these startup pulses for the
synchronous MOSFET is internally programmed.
Figure 5 shows a series of 32, 16, 8 startup
pulses.
Fig. 6. Theoretical operation waveforms
during soft-start
Fig. 4. Pre-Bias startup
06/18/09
12
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